Analog IC Reliability in Nanometer CMOS by Elie Maricau & Georges Gielen

Author:Elie Maricau & Georges Gielen
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

5.2.2.1 Simulation Flow

Figure 5.2 depicts a schematic representation of the deterministic reliability simulation flow. At the input of the simulator, the user has to provide a netlist, a stress bench and a test bench :The netlist describes the circuit under test. This circuit can consist of multiple subcircuits. Through additional statements in the netlist, the user can decide to let the entire circuit age or only a subset of transistors or subcircuits.

The stress bench describes the input voltages and currents applied to the circuit during normal operation of the circuit. Also, it can be used to emulate an accelerated life test at a larger than nominal voltage and/or temperature. The latter is useful to determine suitable input conditions (i.e. test vectors) for prototype testing in a lab environment. The stress bench has to contain a transient analysis to extract accurate stress voltages on every node in the circuit.

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